Fast Redundancy Elimination Using High-Level Structural Information from Esterel - ENSMP_DR Accéder directement au contenu
Rapport Année : 2001

Fast Redundancy Elimination Using High-Level Structural Information from Esterel

Résumé

Esterel programs and SyncCharts hierarchical automata are compiled into flat sequential circuits. The current compiling process often generates too many latches and gates. We propose a compositional technique based on structural information that efficiently removes redundant latches and gates, without adding extra logic. The transformation works in linear time and gives good practical results. The simplified circuit can be used for simulation, verification, and optimisation.
Fichier principal
Vignette du fichier
RR-4330.pdf (298.49 Ko) Télécharger le fichier

Dates et versions

inria-00072257 , version 1 (23-05-2006)

Identifiants

  • HAL Id : inria-00072257 , version 1

Citer

Dumitru Potop-Butucaru. Fast Redundancy Elimination Using High-Level Structural Information from Esterel. RR-4330, INRIA. 2001. ⟨inria-00072257⟩
97 Consultations
133 Téléchargements

Partager

Gmail Facebook X LinkedIn More